1. Field of the Invention
The invention generally relates to accessing memory devices and, more particularly, to transferring data from memory arrays to external data pads of memory devices, such as doubled data rate (DDR) dynamic random access memory (DRAM) devices.
2. Description of the Related Art
The evolution of sub-micron CMOS technology has resulted in an increasing demand for high-speed semiconductor memory devices, such as dynamic random access memory (DRAM) devices, pseudo static random access memory (PSRAM) devices, and the like. Herein, such memory devices are collectively referred to as DRAM devices.
Some types of DRAM devices have a synchronous interface, generally meaning that data is written to and read from the devices in conjunction with a clock pulse. Early synchronous DRAM (SDRAM) devices transferred a single bit of data per clock cycle (e.g., on a rising edge) and are appropriately referred to as single data rate (SDR) SDRAM devices. Later developed double-data rate (DDR) SDRAM devices included input/output (I/O) buffers that transfer a bit of data on both rising and falling edges of the clock signal, thereby doubling the effective data transfer rate. Still other types of SDRAM devices, referred to as DDR-II SDRAM devices, transfer two bits of data on each clock edge, typically by operating the I/O buffers at twice the frequency of the clock signal, again doubling the data transfer rate (to 4× the SDR data transfer rate).
Data read out from such DDR devices is often held in first-in first-out (FIFO) structures that receive the data from the memory arrays and drive the data out onto external data lines. Input and output pointers are typically used to determine (or “point to”) a FIFO location to which data is to be input to or output from the FIFO, respectively. These pointers are typically derived from a DATA_READY signal that is essentially generated as a prediction of when the data should be valid at the FIFO, based on predicted delay through components in the data path. The output pointers ensure the synchronous requirements of data output from the DRAM are satisfied.
Timing of the input pointer signals is critical, as these signals control the latching of data into the FIFOs. If these pointer signals arrive too early, they can close the latches before the data signals are valid at the FIFOs. On the other hand, if these pointer signals arrive too late, these signals could latch data from a following READ access instead of the data from the current READ access. In conventional devices, data is input into the FIFOs at the same rate it is output onto the external data lines. As a result, input pointers are changed at the same rate as output pointers. Unfortunately, as operating speeds increase for DDR (and later generation) DRAM devices, it becomes more and more difficult to meet input pointer timing requirements.
Accordingly, there is a need for an improved methods and apparatus for operating data FIFOs to transfer data from DRAM memory arrays to external data pads.